1. Field
Exemplary embodiments of the present invention relate to an integrated circuit design, and more particularly, to a boot-up operation for a programmable storage cell array included in an integrated circuit.
2. Description of the Related Art
FIG. 1 is a block diagram illustrating a conventional memory device performing a repair operation.
Referring to FIG. 1, the memory device includes a memory cell array 110, a row circuit 120, and a column circuit 130. The memory cell array 110 includes a plurality of memory cells. The row circuit 120 is configured to activate a row (or a word line) selected by a row address R_ADD. The column circuit 130 is configured to access, for example, read or write, data of a column (or a bit line) selected by a column address C_ADD.
A row fuse circuit 140 is configured to store a row address corresponding to a defective memory cell within the memory cell array 110 as a repair row address REPAIR_R_ADD. A row comparator 150 is configured to compare the repair row address REPAIR_R_ADD stored in the row fuse circuit 140 to a row address R_ADD inputted from the outside the memory device. When the repair row address REPAIR_R_ADD is identical with the row address R_ADD, the row comparator 150 controls the row circuit 120 to activate a redundancy row (or a redundancy word line) instead of a row designated by the row address R_ADD.
A column fuse circuit 160 is configured to store a column address corresponding to a defective memory cell within the memory cell array 110 as a repair column address REPAIR_C_ADD. A column comparator 170 is configured to compare the repair column address REPAIR_C_ADD stored in the column fuse circuit 160 with a column address C_ADD inputted from the outside the memory device. When the repair column address REPAIR_C_ADD is identical with the column address C_ADD, the column comparator 170 controls the column circuit 130 to access a redundancy column (or a redundancy bit line) instead of a column designated by the column address C_ADD. For reference, in the FIG. 1, “DATA” denotes data or data pads.
Conventionally, laser fuses has been mainly used as the fuse circuits 140 and 160. The laser fuse stores a logic high data or a logic low data depending on whether the fuse is cut or not. The laser fuse may be programmed in a wafer state, and may not be programmed after a wafer is mounted in a package. Furthermore, the laser fuses may not be designed with a small area due to the limit in a line pitch.
In order to overcome such concerns, as disclosed in U.S. Pat. Nos. 6,904,751, 6,777,757, 6,667,902, 7,173,851, and 7,269,047, programmable storage cell array circuit, such as an E-fuse array circuit, a NAND flash memory, a NOR flash memory, a magnetic random access memory (MRAM), a spin transfer torque magnetic random access memory (STT-MRAM), a resistive random access memory (ReRAM), or a phase change random access memory (PCRAM), is included into the memory device, and repair information, including, for example, fail addresses, is stored in the programmable storage cell array circuit.
FIG. 2 is a block diagram illustrating a conventional memory device including a programmable storage cell array circuit for storing repair information.
Referring to FIG. 2, the memory device includes a plurality of memory banks BK0 to BK3, a plurality of register units 210_0 to 210_3 provided for the respective memory banks BK0 to BK3 to store repair information, and a programmable storage cell array circuit 201.
The programmable storage cell array circuit 201 replaces the fuse circuits 140 and 160 shown in FIG. 1. The programmable storage cell array circuit 201 stores the repair information corresponding to all of the memory banks BK0 to BK3, including, for example, fail addresses. The programmable storage cell array circuit 201 may include any one of an E-fuse array circuit, a NAND flash memory, a NOR flash memory, an MRAM, a STT-MRAM, a ReRAM, and a PCRAM.
The register units 210_0 to 210_3 provided for the respective memory banks BK0 to BK3 may store the repair information to be stored in the corresponding memory banks. The register unit 210_0 may store the repair information regarding the memory bank. BK0, and the register unit 210_2 may store the repair information regarding the memory bank BK2. The register units 210_0 to 210_3 each may include latch circuits, and may store the repair information only while power is supplied. The repair information to be stored in the register units 210_0 to 210_3 may be transmitted from the programmable storage cell array circuit 201. The programmable storage cell array circuit 201 transmits the repair information stored from the time of activation of a boot-up enable signal BOOTEN to the register units 210_0 to 210_3.
Since the programmable storage cell array circuit 201 is configured in an array form, a predetermined time is required to call data stored in the programmable storage cell array circuit 201. Since the data may not be immediately called, the data stored in the programmable storage cell array circuit 201 may not be directly used to perform a repair operation. Thus, the repair information stored in the programmable storage cell array circuit 210 is transmitted and stored into the register units 210_0 to 210_3, and the data stored in the register units 210_0 to 210_3 are used for the repair operation of the memory banks BK0 to BK3. An operation of transmitting the repair information stored in the programmable storage cell array circuit 201 to the register units 210_0 to 210_3 is referred to as a boot-up operation. After the boot-up operation is completed, the memory device may repair a defective cell, and start performing a normal operation.
The boot-up operation is performed while an operation of reading data stored in the programmable storage cell array circuit 201 is repeated a predetermined number of times. For example, several to tens of thousands of read operations is to be performed according to the capacity of the programmable storage cell array circuit 201 and the capacities of the register units 213_0 to 210_3 until the boot-up operation is completed. Since the boot-up operation is to be completed for the memory device to normally operate, it may be important to reduce the time of the boot-up operation.